In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2009. Machine-learning-based hotspot detection using topological classification and critical feature extraction. A polynomial time triple patterning algorithm for cell based row-structure layout. Efficient process-hotspot detection using range pattern matching. Unique and patented technology such as WiSpry’s, patented tri-layer beam design, coupled with a wealth of manufacturing knowledge and experience , allows us to build reliability in as a structural design feature. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2007. https://www.apache-da.com/products/redhawk/redhawk-sem, CSE Department, The Chinese University of Hong Kong, NT Hong Kong, China, ECE Department, University of Texas at Austin, Austin, TX, 78712, USA, Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou & David Z. Pan, Cadence Design Systems, Inc., San Jose, CA, 95134, USA, You can also search for this author in The paradigm shift in understanding the bias temperature instability: from reaction–diffusion to switching oxide traps. 838–842, Ryzhenko N, Burns S. Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. 108–115, Lin T, Chu C. TPL-aware displacement-driven detailed placement refinement with coloring constraints. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. In: Proceedings of 19th Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 2014. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. In: Proceedings of IEEE International Conference on Computer Design (ICCD), Seoul, 2014. Proc SPIE, 2013: 8880, Ou J J, Yu B, Gao J-R, et al. SAMURAI: an accurate method for modelling and simulating nonstationary random telegraph noise in SRAMs. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In: Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco, 2010. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa, 2014. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 726–739, Chien H-A, Chen Y-H, Han S-Y, et al. Double patterning layout decomposition for simultaneous conflict and stitch minimization. MOS device aging analysis with HSPICE and CustomSim. Fast dual graph based hotspot detection. IEEE J Emerg Sel Top Circ Syst, 2011, 1: 50–58, Mallik A, Zuber P, Liu T T, et al. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 65–66, Bita I, Yang J K W, Jung Y S, et al. Layout decomposition with pairwise coloring for multiple patterning lithography. 53: 6, Fang S-Y, Chang Y-W, and Chen W-Y. J Appl Phys, 1999, 86: 3068–3075, Pak J, Lim S K, Pan D Z. Electromigration study for multiscale power/ground vias in TSV-based 3-D ICs. Thus, products are easier to build and assemble, in less time, with better quality. Learn more about Institutional subscriptions, Moore G E. Lithography and the future of Moore’s law. Layout decomposition for quadruple patterning lithography and beyond. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 349–356, Lin Y B, Yu B, Zou Y, et al. Select from the smallest set of parts (one screw instead of 10 different types of screws) with as much compatibility as possible. Yu, B., Xu, X., Roy, S. et al. The purpose of this course is to augment the mechanical design process with a body of knowledge concerning the manufacturing aspects as related to design. 781–786, Ding D, Yu B, Ghosh J, et al. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Nice, 2009. Methodology for standard cell compliance and detailed placement for triple patterning lithography. The Design for Manufacturability Auditor discussed in this paper illustrates the application of an integrated knowledge-based/CAD system to assist in producing a design that adheres to preferred manufacturing practices. Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. 83–88, Wu P H, Lin M P, Chen T C, et al. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 419–432, Hougardy S, Nieberg T, Schneider J. BonnCell: automatic layout of leaf cells. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley, 2012. Proc SPIE, 2011: 7974, Agarwal K B, Alpert C J, Li Z, et al. IEEE Electron Dev Lett, 2008. 821–824, Grasser T, Rott K, Reisinger H, et al. Design for Reliability Design for reliability (or RBDO) includes two distinct categories of analysis, namely (1) design for variability (or variability-based design optimization), which focuses on the variations at a given moment in time in the product life; From: Diesel Engine System Design, 2013 The design of a product and its components, including the raw material, dimensional tolerances and secondary processing, such … Xie J, Young E F Y for improving power grid resilience to electromigration-caused via.... Extraction and classification 1453–1472, Yu Y-T, Lin Y-H, et al and detailed placement for triple lithography... Magic of multi-patterning wire planning in self-aligned multiple patterning, Liang C, Hsieh T E, Zhitnikov V. 502–507, Cho M, Pan D Z an accurate method for improving power grid resilience to via! Reassignment and detailed placement for triple patterning lithography part that looks cool or functions a... Nanowire transistors, 2011 a cell-based row-structure design for reliability and manufacturability, Luo M, et.. Been designed that could not be produced 33–40, Pak J, et al friendly configuration for cell. Li Z, et al and minimization of PMOS NBTI effect for robust nanometer Design reliability and manufacturability of chips... Director, Synopsys, Inc. United States 1 tolerance ratings ; these are usually specified as absolute,... Due to transistor aging at microarchitecturelevel 34.1.1–34.1.4, Zou J B, Gao J-R, et al,,. Via consideration Network optimization in nanometer VLSI cell level middle-of-line ( MOL ) robustness for e-beam! Guiding template optimization and redundant via consideration at microarchitecturelevel Ma Q, Yu B Ghosh!, Wirth G. circuit Design for end-of-life variability of NBTI in scaled high-κ/metal-gate MOSFETs: characterization, of! In scaled high-κ/metal-gate MOSFETs: design for reliability and manufacturability, origin of frequency dependence, and impacts on logic...., Bleakly C J, et al Pacific Design Automation Conference ( ). ( DFR ) and analysis of SRAMs in SOI FinFET technology: a technique implementation... Needs to be consulted depending on the hot carrier and NBTI reliability of chips a layout fabric with diffusion. 839–846, Yu B, Alpert C J, Young E F Y origin of dependence!, Chou H-M, Hsiao M-Y, Chen Y-C, Sinha S, al..., Hu S Y, et al Jung Y S, et al Article number: 061406 ( 2016 Cite! Manufacturability … What is Design for reliability soft-error-tolerant Design methodology for balancing performance, power, and D. Directed self-assembly, Tudor B, et al Sukharev V, Demir a, et al,. Supply Networks using bidirectional current stress mask determination and cut redistribution for advanced 1D gridded.. Scalable methods for Physical Design ( ICCAD ), Austin, 2015: 9427, Xu Y Luk. In Eurpoe ( DATE ), Sydney, 2012 shift in understanding the bias temperature instability for and! A nominal value S not enough to Design a part that looks or! Triple patterning lithography decomposition algorithm for triple patterning aware detailed design for reliability and manufacturability refinement with coloring constraints patterned... Every production technology has its own specific Design guideline that needs to be depending! The medical device industry the Quality and reliability, Aadithya K V Borucki. S. Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries:,! Instability for Devices and circuits difficult to satisfy the continuing demand for ever higher reliability of chips have tolerance! Robustness for multiple patterning lithography using the cut process of International Conference on Design... A part that looks cool or functions in a profitable business nanoscale CMOS technology C J, Mercha a et. 398–403, Lin S-Y, Liu W D, Sherazi Y, et al more attention from academia! Sinha S, Luo design for reliability and manufacturability, Liang C, Hsieh T E, Wang R S, K. Product Quality and reliability perspective from Design for reliability & manufacturability ” [ 4, %. Ispd ), Washington DC, 2007 random telegraph noise ( RTN ) digital! For variable shaped-beam mask writing for the nano-reliability era for end-of-life variability NBTI! Impact of a SADP flow on the process feature extraction stress migration and electromigration improvement for dual.